Technical Field
The present invention generally relates to verifying an integrated circuit design. More particularly, the present invention relates to wafer-level electrical testing of a circuit for optical proximity correction and/or etch bias.
Background Information
In circuit design, the controlling factor determining the resistance of a line is its width, what is known as the critical dimension. Currently, integrated circuit fabrication includes failure analysis, the results of which provide useful, but limited, information (i.e., failure or success).
Thus, a need exists for more robust testing providing more useful information with regard to fundamental patterns in circuit design and process response to those patterns.